The 3nm node will make use of FinFET know-how due to its maturity, reliability and cost-efficiency. Wei additionally claimed that the N3 could have a density enchancment of 1.7x over N5 (5nm course of node), whereas estimates supplied by WikiChip suggests the previous ought to supply a cell-level density of just below 300 million transistors per sq. millimeter. In phrases of efficiency and pace, TSMC claims that N3 will present 10-15 p.c pace enchancment over N5 at iso-power or 25-30 p.c energy discount at iso-speed.
The first concrete information about TSMC’s 3nm know-how comes virtually precisely a yr after the corporate’s 5nm node entered threat manufacturing final yr. According to Wei, N5 manufacturing is now being ramped up with good yield. It is anticipated to ship round 1.8x enchancment in density together with 15 p.c greater pace at iso-power or, alternatively, 30 p.c decrease energy consumption on the similar pace over N7.
The firm expects N5 to contribute about 10 p.c of whole wafer income in 2020 at the same time as its flagship 7nm course of node continues to stay the highest canine within the foreseeable future. In the primary quarter, N7 contributed round 35 p.c of the corporate’s revenues, whereas each 16-nanometer and 10-nanometer income share dropped marginally due to weaker demand for older SoCs.